Fairchild technologies deliver power, speed, and precision in ever-smaller packages

   Delivering cutting edge power, interface, and optoelectronic products requires that Fairchild invest in emerging technologies improving our product performance no matter where they go. We do this by focusing our research and development in both silicon and packaging technologies that benefit all of our products.

   Take, for example, our industry leading PowerTrench silicon process. In every Power MOSFET, the key performance parameter is R_DS or "on resistance." The silicon area or die size of these chips is important, since they need to fit into tiny circuit boards within cellular phones and palm-sized appliances. Fairchild's PowerTrench process etches trenches into the silicon surface, then builds tiny electronic gates into the walls of these trenches. This approach is superior to traditional planar processing because it enables us to continuously minimize R_DS and silicon area, allowing better power handling with less generated heat and lower system voltage drops. Fairchild is so good at this that we are already shipping our second generation of PowerTrench products, and have development underway for the third and fourth generations.

   In addition to PowerTrench, Fairchild continues to optimize our multi-purpose portfolio of CMOS, BiCMOS, Bipolar, and BCDMOS processes, all used in our expanding line of power and interface products, and all capable of being manufactured in wafer fabrication lines throughout the company. We design these processes to provide high performance and flexibility at low costs, to achieve efficient factory utilization rates while continuing to offer a wide array of new products.
   
   Process development is only half the solution. In many cases we need to combine our advanced processes and circuit designs with packaging techniques to provide even better performance. This is especially true in our Power MOSFET products, where reducing the resistance through the package interconnect is critical to maintaining device characteristics. We've solved this problem by using bump bond technology on our newest chip scale packages. Bump bond attachment allows us to eliminate wire bonds, improving package performance and allowing package sizes to approach the area of the silicon itself.

   We continue to shrink package sizes for all our logic, analog and optoelectronic lines as well, including the industry's first ball grid array (BGA) packages for bus switch products. The real advantage of Fairchild's package development strategy lies in our ability to quickly reuse our technology. Because our products share similar process technologies, pin count requirements, and assembly test facilities, we can quickly extend innovative technology developed for one product line to another, maximizing our investment.

   As Fairchild's products are designed into smaller and smaller circuit boards for portable products like personal digital appliances, handheld computers, digital cameras, and cellular phones, miniaturizing our packages becomes as important as optimizing our circuit designs and silicon processes. That's why we continue to do all of our own package development. Because no matter where you go... whether you're talking on your cellular phone...listening to MP3 music files... investing on the Internet...or using any of the other electronic appliances that are part of your life every day...there we are.